1Field of the Invention
The present invention relates to phase-locked loops (PLLs), and more particularly to a frequency synthesizer serving, in a digital PLL, as a voltage controlled oscillator.
2. Discussion of the Related Art
FIG. 1 schematically represents a conventional PLL architecture. The PLL includes a voltage controlled oscillator (VC0) 10 providing a frequency NF to an N-divider 12. A phase comparator 14 receives the output frequency F from divider 12 and a reference frequency Fref. The phase comparator 14 provides a phase error signal e to a filter 16 whose output c controls the oscillator 10. In steady state, the phase and frequency of signal F are locked on signal Fref. In common applications, for example in the horizontal scanning of a television set, the scanning frequency F is approximately 15 kHz, the frequency NF is approximately 12 MHz (N=768), and filter 16 is a low-pass filter whose cut-off frequency is a few hundred hertz.
At present, the trend is to realize all the PLL elements in the form of digital circuits. This avoids the use of high value capacitors that are difficult to integrate, renders the elements programmable, and simplifies the design operations by allowing use of standard blocks in MOS or CMOS technologies.
FIG. 2 represents an embodiment of a digital VC0 10, when filter 16 is a digital filter and provides a digital correction signal C. The digital equivalent of a controlled oscillator is a frequency synthesizer. To generate signal NF, generally, a clock signal Fh, having a frequency higher than the frequency of signal NF, is divided by a programmable divider 10-1. Divider 10-1 receives as programmation information the digital correction signal C. The higher the frequency Fh is with respect to the synthesized frequency NF, the better the precision or resolution of this synthesized frequency is.
In television horizontal scanning systems, signal NF is approximately 12 MHz. The highest frequency Fh that can be obtained with common technologies is within the range of 100 to 300 MHz. The frequency Fh must be particularly steady. One of the methods to obtain a high steady frequency is to use a frequency multiplier that, in fact, is an auxiliary analog PLL. The analog PLL includes a controlled oscillator 10-2 providing the frequency Fh to the programmable divider 10-1 and to a divider 10-3. A phase comparator 10-4 receives the output of divider 10-3 and the output of a quartz oscillator 10-5. The output e2 of comparator 10-4 is provided to a filter 10-6 that in turn provides a correction signal c2 to the controlled oscillator 10-2.
The above-described frequency multiplier PLL operates at a particularly high frequency. Accordingly, the capacitors required for the construction of the PLL, more particularly the capacitors of filter 10-6, are small-size and integrable capacitors. The clock frequency Fh is equal to the frequency of oscillator 10-5 multiplied by the dividing ratio of divider 10-3. The oscillator 10-5 is not entirely integrable but it is generally not necessary. In fact, the signal of this oscillator may be an arbitrary clock signal that is very frequently available in integrated circuits including the digital PLL. The required frequency Fh is obtained by suitably selecting the dividing ratio of divider 10-3.
If it is desired to obtain a frequency NF having a good resolution, the dividing ratio K of divider 10-1 must be high, or alternatively, the frequency Fh must be much higher than frequency NF. However, the frequency Fh is in practice limited to a few hundred MHz. With a frequency Fh of 220 MHz, for example, the dividing ratio is small, within 18 and 19, to obtain a signal NF of approximately 12 MHz in a television horizontal scanning PLL.
FIG. 3 represents a conventional digital frequency synthesizer for dividing a high frequency Fh by a noninteger number. The programmation data C is partitioned into an integer portion Int(C)=K, corresponding, for example, to a few high weight bits of data C, and into a fractional portion Frac(C) corresponding to the remaining low weight bits of data C. The integer portion K is provided to a first input of an adder 20. Adder 20 provides to a conventional programmable divider 22 the sum of the integer portion K and of a carry bit Cout that is provided by a second adder 24. The carry bit Cout is provided either to a second input of adder 20 or to a carry input of adder 20, the second input of adder 20 then receiving value 0. The divider 22 provides the signal NF to be synthesized by dividing the high frequency Fh by K (or by a ratio corresponding to K).
The fractional portion Frac(C) of data C is provided to a first input of adder 24. A register 25 receives the output of adder 24, and the content A of register 25 is provided to a second input of adder 24. The register 25 is enabled at the rate of signal NF. The adder 24 and register 25 constitute a so-called "accumulator" designated by reference numeral 26.
Initially, the accumulator 26 (i.e. the content A of register 25) is at "0". The register 25 receives at the rate of signal NF the sum of its content A and of the fractional portion Frac(C). The accumulator 26 is designed so that it can overflow when the sum of the successive fractional portions reaches a value corresponding to one unit of the dividing ratio K. At the moment when the accumulator overflows, the value K provided to the programmable divider is incremented by 1 only during one cycle of signal NF.
With this configuration, the high frequency Fh is sometimes divided by K, sometimes divided by. K+1, the ratio between the number of times frequency Fh is divided by K+1 and the number of times it is divided by K being equal to the fractional portion of data C. Thus, the average frequency of the synthesized signal NF is equal to the frequency Fh divided by the desired fractional number.
The use of the synthesizer of FIG. 3 in a digital PLL provides a good precision for the frequency of the signal F generated by the PLL, since, to obtain the signal F, the signal NF and its frequency error are divided by a high number (approximately 768 in the example of horizontal scanning of a television set) by divider 12.
However, the frequency F generated by the PLL exhibits a jitter equal to the period of the high frequency Fh. In some applications, as for example in the horizontal scanning of a television set, this jitter cannot be seen on the screen with a maximum 220-MHz frequency Fh. In contrast, if the PLL is used in monitors having a high scanning frequency, the jitter becomes visible.